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IEICE SEARCH SYSTEM

Masakazu YAMASHINA

An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems Toshiaki INOUE Takashi MANABE Sunao TORII Satoshi MATSUSHITA Masato EDAHIRO Naoki NISHI Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/08/01 Vol. E84-C No. 8 pp. 1014-1020 Type of Manuscript: INVITED PAPER (Special Issue on Silicon Nanodevices) Category: Keyword: SIMD, multiplier, embedded microprocessor, on-chip multiprocessor, area-efficiency,
	Summary \| Full Text:PDF (2.5MB)

A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges Koichiro MINAMI Masayuki MIZUNO Hiroshi YAMAGUCHI Toshihiko NAKANO Yusuke MATSUSHIMA Yoshikazu SUMI Takanori SATO Hisashi YAMASHIDA Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 220-228 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: delay-locked loop, infinite phase capture ranges, variable delay line, dynamic phase detector,
	Summary \| Full Text:PDF (1.2MB)

Device-Deviation Tolerant Elastic-Vt CMOS Circuits with Fine-Grain Power Control Capability Masayuki MIZUNO Hitoshi ABIKO Koichiro FURUTA Isami SAKAI Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/20 Vol. E81-C No. 9 pp. 1463-1472 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: low-threshold voltage, leakage current, supply-voltage fluctuation, supply-voltage control, low power dissipation,
	Summary \| Full Text:PDF (972.4KB)

A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO Masayuki MIZUNO Koichiro FURUTA Takeshi ANDOH Akira TANABE Takao TAMURA Hidenobu MIYAMOTO Akio FURUKAWA Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/20 Vol. E80-C No. 12 pp. 1560-1571 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: phase-locked loop, low voltage, low jitter, fast-lock time,
	Summary \| Full Text:PDF (978.6KB)

Compact Realization of Phase-Locked Loop Using Digital Control Masanori IZUMIKAWA Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/20 Vol. E80-C No. 4 pp. 544-549 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: phase-locked loop (PLL), digital control, D/A converter,
	Summary \| Full Text:PDF (363KB)

A Current Direction Sense Technique for Multiport SRAM's Masanori IZUMIKAWA Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/20 Vol. E79-C No. 7 pp. 957-962 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
	Summary \| Full Text:PDF (379.6KB)

Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI Tomofumi IIMA Masayuki MIZUNO Tadahiko HORIUCHI Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/20 Vol. E79-C No. 7 pp. 942-947 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Interface Circuits Keyword:
	Summary \| Full Text:PDF (441.8KB)

A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/12/20 Vol. E77-C No. 12 pp. 1951-1956 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs) Category: Processor Interfaces Keyword: electronic circuits, clock generator, PLL, frequency multiplication, VCO, VCO gain, jitter, pull-in range, CMOS, VSP,
	Summary \| Full Text:PDF (693KB)

An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors Masakazu YAMASHINA Hachiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/10/20 Vol. E75-C No. 10 pp. 1181-1187 Type of Manuscript: Special Section PAPER (Special Issue on Microprocessors) Category: Low-Voltage Operation Keyword: current mode logic, low power, high speed, MOS,
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