Masayuki MIZUNO


A Duobinary Signaling for Asymmetric Multi-Chip Communication
Koichi YAMAGUCHI Masayuki MIZUNO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 619-626
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
partial responseDuobinary signalingsymbol-rate clock recoveryoversampled equalizer
 Summary | Full Text:PDF(2.2MB)

Dicode Partial Response Signaling over Inductively-Coupled Channel
Koichi YAMAGUCHI Masayuki MIZUNO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 613-618
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
inductively coupledpartial responsecurrent-mode driveradaptive equalization
 Summary | Full Text:PDF(1.2MB)

A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests
Shunichi KAERIYAMA Mikihiro KAJITA Masayuki MIZUNO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1  pp. 102-109
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock generatorduty ratiofrequency synthesisI/Q balancejittertiming margin
 Summary | Full Text:PDF(2.3MB)

LSI On-Chip Optical Interconnection with Si Nano-Photonics
Junichi FUJIKATA Kenichi NISHI Akiko GOMYO Jun USHIDA Tsutomu ISHI Hiroaki YUKAWA Daisuke OKAMOTO Masafumi NAKADA Takanori SHIMIZU Masao KINOSHITA Koichi NOSE Masayuki MIZUNO Tai TSUCHIZAWA Toshifumi WATANABE Koji YAMADA Seiichi ITABASHI Keishi OHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/02/01
Vol. E91-C  No. 2  pp. 131-137
Type of Manuscript:  Special Section PAPER (Special Section on Silicon Photonics Technologies and Their Applications)
Category: INVITED
Keyword: 
optical interconnectLSISi nano-photonicsSiON waveguideSi nano-photodiodesurface plasmon antennaTIA-less optical clock circuit
 Summary | Full Text:PDF(1.7MB)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link
Kiichi NIITSU Noriyuki MIURA Mari INOUE Yoshihiro NAKAGAWA Masamoto TAGO Masayuki MIZUNO Takayasu SAKURAI Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4  pp. 829-835
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Analog and Communications
Keyword: 
low powerdaisy chaininductive couplingwide bandwidth
 Summary | Full Text:PDF(1.7MB)

Solid-Electrolyte Nanometer Switch
Naoki BANNO Toshitsugu SAKAMOTO Noriyuki IGUCHI Hisao KAWAURA Shunichi KAERIYAMA Masayuki MIZUNO Kozuya TERABE Tsuyoshi HASEGAWA Masakazu AONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1492-1498
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: INVITED
Keyword: 
solid-electrolyteelectrochemical reactionion diffusionprogrammable logic
 Summary | Full Text:PDF(1MB)

A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges
Koichiro MINAMI Masayuki MIZUNO Hiroshi YAMAGUCHI Toshihiko NAKANO Yusuke MATSUSHIMA Yoshikazu SUMI Takanori SATO Hisashi YAMASHIDA Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 220-228
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
delay-locked loopinfinite phase capture rangesvariable delay linedynamic phase detector
 Summary | Full Text:PDF(1.2MB)

Device-Deviation Tolerant Elastic-Vt CMOS Circuits with Fine-Grain Power Control Capability
Masayuki MIZUNO Hitoshi ABIKO Koichiro FURUTA Isami SAKAI Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1463-1472
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
low-threshold voltageleakage currentsupply-voltage fluctuationsupply-voltage controllow power dissipation
 Summary | Full Text:PDF(972.4KB)

A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO
Masayuki MIZUNO Koichiro FURUTA Takeshi ANDOH Akira TANABE Takao TAMURA Hidenobu MIYAMOTO Akio FURUKAWA Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1560-1571
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
phase-locked looplow voltagelow jitterfast-lock time
 Summary | Full Text:PDF(978.6KB)

Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI
Tomofumi IIMA Masayuki MIZUNO Tadahiko HORIUCHI Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C  No. 7  pp. 942-947
Type of Manuscript:  Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Interface Circuits
Keyword: 
 Summary | Full Text:PDF(441.8KB)