IEICE SEARCH SYSTEM

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IEICE SEARCH SYSTEM

Tetsushi KOIDE

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching Fengwei AN Tetsushi KOIDE Hans Jürgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/09/01 Vol. E95-D No. 9 pp. 2327-2338 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: multi-prototype learning system, K-means clustering, software-hardware cooperation, one nearest neighbor (1-NN), FPGA-implemented coprocessor, nearest euclidean distance searching,
	Summary \| Full Text:PDF (1MB)

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems Takeshi KUMAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Masaharu TAGAMI Masakatsu ISHIZAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/09/01 Vol. E94-D No. 9 pp. 1742-1754 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: matrix-processing architecture, SIMD, bit-serial and word-parallel, CAM, table-lookup coding, cryptographic algorithm, AES,
	Summary \| Full Text:PDF (1.1MB)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Takayuki GYOHTEN Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1409-1418 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: content addressable memory, CAM, matrix-processing architecture, SIMD, bit-serial and word-parallel, table-lookup coding, DCT, Huffman coding, JPEG,
	Summary \| Full Text:PDF (614.1KB)

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words Koh JOHGUCHI Hans Jurgen MATTAUSCH Tetsushi KOIDE Tetsuo HIRONAKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/11/01 Vol. E90-C No. 11 pp. 2157-2160 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: multi-port memory, unified cache, SRAM, CMOS,
	Summary \| Full Text:PDF (979.6KB)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/08/01 Vol. E90-D No. 8 pp. 1312-1315 Type of Manuscript: LETTER Category: Image Processing and Video Processing Keyword: DCT, fast DCT, matrix-processing engine, SIMD, bit-serial and word-parallel,
	Summary \| Full Text:PDF (486.1KB)

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories Md. Anwarul ABEDIN Yuki TANAKA Ali AHMADI Shogo SAKAKIBARA Tetsushi KOIDE Hans Jurgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/06/01 Vol. E90-A No. 6 pp. 1240-1243 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: associative memory, pattern matching, fully-parallel search, k-nearest-matches,
	Summary \| Full Text:PDF (393.7KB)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer Takeshi KUMAKI Yasuto KURODA Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 334-345 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: content addressable memory, CAM, Huffman coding, parallel processing, pipeline, code word table,
	Summary \| Full Text:PDF (2.1MB)

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory Takeshi KUMAKI Yutaka KONO Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 346-354 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: multiport, content addressable memory, CAM, parallel processing, SIMD, categorization, bit parallel block parallel, table-lookup-coding, Huffman coding,
	Summary \| Full Text:PDF (1.6MB)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC Hideyuki NODA Katsumi DOSAKA Hans Jurgen MATTAUSCH Tetsushi KOIDE Fukashi MORISHITA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1612-1619 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: soft error, ECC, TCAM, embedded, DRAM,
	Summary \| Full Text:PDF (1.2MB)

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation Takashi MORIMOTO Hidekazu ADACHI Osamu KIRIYAMA Tetsushi KOIDE Hans Jurgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1299-1302 Type of Manuscript: LETTER Category: Image Processing and Video Processing Keyword: image segmentation, real-time image processing, parallel processing, LSI implementation,
	Summary \| Full Text:PDF (1.3MB)

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features Kazunari INOUE Hideyuki NODA Kazutami ARIMOTO Hans Jurgen MATTAUSCH Tetsushi KOIDE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/06/01 Vol. E88-C No. 6 pp. 1332-1342 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: CAM, TCAM, signature-matching, network security,
	Summary \| Full Text:PDF (2.1MB)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 622-629 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Memory Keyword: CMOS, Ternary CAM, network, refresh,
	Summary \| Full Text:PDF (1.3MB)

Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation Takashi MORIMOTO Yohmei HARADA Tetsushi KOIDE Hans Jurgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/02/01 Vol. E87-D No. 2 pp. 500-503 Type of Manuscript: LETTER Category: Image Processing, Image Pattern Recognition Keyword: image segmentation, pixel-parallel processing, cell-network, LSI implementation, digital CMOS circuit,
	Summary \| Full Text:PDF (640.3KB)

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation Shinya YAMASAKI Shingo NAKAYA Shin'ichi WAKABAYASHI Tetsushi KOIDE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2775-2784 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: floorplanning, timing-driven layout, buffer insertion, wire sizing, simulated annealing,
	Summary \| Full Text:PDF (392.5KB)

An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints Jun'ichiro MINAMI Tetsushi KOIDE Shin'ichi WAKABAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/20 Vol. E83-A No. 12 pp. 2569-2576 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Synthesis Keyword: circuit partitioning, iterative improvement, FM method, timing constraint, path-cut number,
	Summary \| Full Text:PDF (477.6KB)

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout Tetsushi KOIDE Shin'ichi WAKABAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/20 Vol. E81-A No. 12 pp. 2476-2484 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Optimization Keyword: building block layout, global routing, pin assignment, timing constraint, simulated evolution,
	Summary \| Full Text:PDF (883.6KB)

Mixed Planar and H-V Over-the-Cell Routing for Standard Cells with Nonuniform Over-the-Cell Routing Capacities Tetsushi KOIDE Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/20 Vol. E79-D No. 10 pp. 1419-1430 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Lauout Synthesis Keyword: over-the-cell routing, non-uniform over-the-cell routing capacity, planar routing, H-V routing, dynamic programming,
	Summary \| Full Text:PDF (1.1MB)

An Efficient Timing-Driven Global Routing Method for Standard Cell Layout Tetsushi KOIDE Takeshi SUZUKI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/20 Vol. E79-D No. 10 pp. 1410-1418 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Lauout Synthesis Keyword: standard cell layout, global routing, timing constraints, slack distribution, 0-1 integer linear programming,
	Summary \| Full Text:PDF (858.2KB)

A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout Tetsushi KOIDE Yoshinori KATSURA Katsumi YAMATANI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/20 Vol. E77-A No. 12 pp. 2053-2057 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: building block layout, floorplanning, relative placement, topological constraint, strong respect, tentative insertion, block reshaping,
	Summary \| Full Text:PDF (388.4KB)

A Graph Bisection Algorithm Based on Subgraph Migration Kazunori ISOMOTO Yoshiyasu MIMASA Shin'ichi WAKABAYASHI Tetsushi KOIDE Noriyoshi YOSHIDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/20 Vol. E77-A No. 12 pp. 2039-2044 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: graph partitioning, heuristic algorithm, Kernighan-Lin algorithm, Fiduccia-Mattheyses algorithm, subgraph migration,
	Summary \| Full Text:PDF (577.4KB)

An Optimal Channel Pin Assignment Algorithm for Hierarchical Building-Block Layout Design Tetsushi KOIDE Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/20 Vol. E76-A No. 10 pp. 1636-1644 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: channel pin assignment, channel routing, channel density, building-block layout,
	Summary \| Full Text:PDF (770.9KB)