Keyword : circuit partitioning


A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5 ; pp. 924-931
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
circuit partitioningtime-multiplexed I/OFPGApin constraint
 Summary | Full Text:PDF(402.5KB)

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies
Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/04/01
Vol. E88-D  No. 4 ; pp. 703-710
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
fault diagnosisIDDQtransistor leakage fault modelmultiple power supplycircuit partitioning
 Summary | Full Text:PDF(487.1KB)

An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints
Jun'ichiro MINAMI Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2569-2576
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis
Keyword: 
circuit partitioningiterative improvementFM methodtiming constraintpath-cut number
 Summary | Full Text:PDF(477.6KB)

A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 494-505
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGAmulti-FPGA systemcircuit partitioningpath delaylogic-block replication
 Summary | Full Text:PDF(895.1KB)

A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1765-1776
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAcircuit partitioninglogic-block replicationnetwork flow
 Summary | Full Text:PDF(904.6KB)

A Parallel BBD Matrix Solution for MIMD Parallel Circuit Simulation
Tetsuro KAGE Junichi NIITSUMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/01/25
Vol. E78-A  No. 1 ; pp. 88-93
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
parallel circuit simulationMIMD parallel computercircuit partitioningbordered-block-diagonal (BBD) matrixLU-decomposition
 Summary | Full Text:PDF(523.4KB)

A Circuit Partitioning Approach for Parallel Circuit Simulation
Tetsuro KAGE Fumiyo KAWAFUJI Junichi NIITSUMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3 ; pp. 461-466
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Modeling and Simulation
Keyword: 
circuit partitioningparallel circuit simulationsubcircuitsinterconnection nodesbordered-block-diagonal (BBD) matrix
 Summary | Full Text:PDF(447.2KB)

An Efficient Hypergraph Bisection Algorithm for Partitioning VLSI Circuits
Yoko KAMIDOI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1272-1279
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hypergraphbisectionnetgraphcircuit partitioning
 Summary | Full Text:PDF(701.4KB)